Cadence IC Virtuoso v6 for PC Windows

Description

Overview of Cadence IC Design Virtuoso Benefits

Cadence Virtuoso is used at CSUS for similar tasks in more advanced classes and graduate student projects in integrated circuit design. An electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Design time savings can range from half a day to several days per block, depending on block complexity.

Cadence Virtuoso custom IC design platform that improves electronic system and IC design productivity. The enhancements affect almost every Virtuoso product, providing system engineers with a robust environment and ecosystem to design, implement and analyze complex chips, packages, boards, and systems.

Cadence made several enhancements to improve analog design and analysis. The Virtuoso Analog Design Environment (ADE) simulation throughput is improved by up to 3x due to enhanced integration with the Cadence Spectre Circuit Simulator, increasing simulation throughput and using advanced analysis to reduce design iterations. Unique capabilities were added to the Virtuoso ADE Verifier to centralize cross-domain electrical specifications so the path to standards compliance (e.g., ISO 26262) is streamlined by approximately 30 percent.

Overview of Cadence IC Design Virtuoso Features

• Advanced layout methodologies and simulation-driven layout improve layout productivity by up to 50%
• Reduces FinFET layout effort by >3X
• Improves Virtuoso ADE simulation throughput by up to 3X
• Reduces design variation analysis time by approximately 20% using advanced statistical algorithms
• Virtuoso ADE Verifier improves path to standards compliance by approximately 30%
• Enhanced Virtuoso System Design Platform with multi-technology and multi-PDK support

System Requirements and Technical Details

• Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0