Cadence PVS (Physical Verification System) v22 for LINUX

Description

Cadence Physical Verification System (PVS) is the premier signoff solution enabling in-design and back-end physical verification, constraint validation, and reliability checking. The system integrates with industry-standard Cadence Virtuoso custom/analog, Cadence Innovus digital design, and mixed-signal flows. This provides you with an end-to-end design and signoff physical verification solution integrated with all Cadence tools. With PVS, you can complete advanced-node design signoff checks (DRC and LVS) with peace of mind. Foundries provide the PVS rule decks, and PVS provides efficient, comprehensive debug tools to reduce debug time and increase productivity. This solution supports advanced process node technologies (such as double patterning, triple patterning, quadruple patterning, 3D-IC, FinFET rules, advanced device extraction, and more), and it extends physical verification technology into design reliability checking and constraint validation. PVS also offers a distributed processing capability that greatly accelerates throughput without requiring specialized hardware. Cadence is a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Features of Cadence PVS

• Programmable Electrical Rule Checker – Enables flexible rule checking for electrical constraints.
• Constraint Validator – Ensures design constraints are met throughout the verification process.
• Predictable Debug Cycle – Streamlines debugging to improve efficiency.
• Interactive Short Locator – Helps quickly identify and resolve shorts in the design.
• Graphical LVS Debug – Provides a visual interface for debugging layout versus schematic (LVS) issues.
• Error Results Visualization and Management – Enhances error tracking and resolution.
• Competitive Performance for Design Throughput – Optimized for high-speed verification.
• Drop-in Compatibility with Industry-Standard Formats – Works seamlessly with existing verification flows