Description
Mentor Graphics (now Siemens EDA) HDL Designer Series (HDS) is a comprehensive electronic design automation (EDA) environment for creating, analyzing, and managing complex hardware designs for field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The 2021 version built upon the existing core functionality to enable a structured design flow for individual engineers and teams.
Core capabilities
- Design creation: HDS 2021 provides multiple design entry methods, including intelligent text, graphical, and tabular editors. Engineers can use:
- Graphical block diagrams to create and edit designs and model hierarchy and connectivity.
- State diagrams for finite state machine modeling.
- Flow charts for sequential process modeling.
- Truth tables for combinatorial logic.
- Design analysis: A suite of analysis tools helps engineers assess the quality of new and reused code.
- Code integrity analysis: Checks for errors within the HDL code.
- Connectivity analysis: Ensures the completeness of connections between modules.
- Design visualization: Provides graphical representations of the design to aid comprehension.
- Automated design checking: HDS includes automated rule checking to enforce design standards and coding guidelines.
- The tool helps find design flaws early, which is less expensive than correcting them later in the design cycle.
- It comes with pre-configured rulesets, including those for safety-critical standards like DO-254.
- Project and flow management: HDS helps manage the design data throughout the development cycle by providing:
- Version management integration: Interfaces with popular version control systems like Subversion and ClearCase.
- Custom flow automation: An open API allows users to create custom scripts and integrate with existing design processes.
- Team collaboration support: Facilitates team-based development by enforcing consistent standards and automating repetitive tasks.
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